1. Field of the Invention
The invention relates generally to systems and methods for reducing the power consumption of logic circuits. More particularly, the invention relates to systems and methods for selectively sending a clock signal to active sections of a circuit thereby reducing power consumption associated with the inactive sections.
2. Related Art
Typical multiplexers are configured to receive a plurality of inputs and to select and output one of those inputs. Multiplexers select one of the inputs according to the value of a received control signal. For example, the nth input may be selected if the value represented by the received control signal is equal to n. A multiplexer may also include a decoder that is configured to receive a coded control signal and to decode the control signal into a decoded control signal having a 1 in the position corresponding to the input that is to be selected and 0 elsewhere. Accordingly, one of the input signals is selected and then output by the multiplexer.
Multiplexers typically contain multiple cells, the number of which is equal to the number of inputs that the multiplexer is configured to receive. Each cell of a multiplexer-and in certain cases, other supporting logic such as latches-is also configured to receive a clock signal that synchronizes the operation of the multiplexer with other parts of the circuit in high-speed applications. Accordingly, each of the cells of the multiplexer and supporting logic are configured to process corresponding input and control signals upon receiving an asserted clock signal. Though only one input is selected at a time (i.e., only one cell of the multiplexer is active at a time), the clock signal is typically provided to all the cells of the multiplexer as well as to corresponding latches and supporting logic.
Regardless of whether cells/logic are active during a clock cycle, the cells/logic present impedance to the clock signal in the form of capacitance. When voltage is applied to a part of a circuit having capacitance, power equal to the product of the capacitance and the voltage squared is required. Because capacitance values in integrated circuits have been steadily increasing as the sizes of the devices and the distances between the wires in the integrated circuits have been decreasing, power losses due to capacitance have been increasing. Each of the cells of a multiplexer and any latches and other logic contribute to an increase in the value of the overall capacitance in the circuit. Power is consumed when a clock signal is asserted to a cell and supporting logic regardless of whether the cell is active.
It would therefore be desirable to provide systems and methods to reduce the power consumption associated with the capacitance in multiplexers and similar circuits.